Fully printed and encapsulated SWCNT-based thin film transistors via a combination of R2R gravure and inkjet printing

From National Research Council Canada

Download	View final version: Fully printed and encapsulated SWCNT-based thin film transistors via a combination of R2R gravure and inkjet printing (PDF, 1 MB)
DOI	Resolve DOI: https://doi.org/10.1021/acsami.6b06838
Author	Search for: Homenick, Christa M.¹; Search for: James, Robert; Search for: Lopinski, Gregory P.²; Search for: Dunford, Jeffrey¹; Search for: Sun, Junfeng; Search for: Park, Hyejin; Search for: Jung, Younsu; Search for: Cho, Gyoujin; Search for: Malenfant, Patrick R. L.¹
Name affiliation	National Research Council of Canada. Security and Disruptive Technologies National Research Council of Canada. Measurement Science and Standards
Format	Text, Article
Journal title	ACS Applied Materials & Interfaces
ISSN	1944-8244 1944-8252
Subject	fully printed; thin film transistor; enriched semiconducting carbon nanotube ink; SWCNT ink formulation; roll-to-roll
Abstract	Fully printed thin film transistors (TFT) based on poly(9,9-di-n-dodecylfluorene) (PFDD) wrapped semiconducting single walled carbon nanotube (SWCNT) channels are fabricated by a practical route that combines roll-to-roll (R2R) gravure and ink jet printing. SWCNT network density is easily controlled via ink formulation (concentration and polymer:CNT ratio) and jetting conditions (droplet size, drop spacing, and number of printed layers). Optimum inkjet printing conditions are established on Si/SiO₂ in which an ink consisting of 6:1 PFDD:SWCNT ratio with 50 mg L⁻¹ SWCNT concentration printed at a drop spacing of 20 μm results in TFTs with mobilities of ∼25 cm² V⁻¹ s⁻¹ and on-/off-current ratios > 105. These conditions yield excellent network uniformity and are used in a fully additive process to fabricate fully printed TFTs on PET substrates with mobility values > 5 cm² V⁻¹ s⁻¹ (R2R printed gate electrode and dielectric; inkjet printed channel and source/drain electrodes). An inkjet printed encapsulation layer completes the TFT process (fabricated in bottom gate, top contact TFT configuration) and provides mobilities > 1 cm² V⁻¹ s⁻¹ with good operational stability, based on the performance of an inverter circuit. An array of 20 TFTs shows that most have less than 10% variability in terms of threshold voltage, transconductance, on-current, and subthreshold swing.
Publication date	2016-09-23
Language	English
Peer reviewed	Yes
NPARC number	23000810
Export citation	Export as RIS
Report a correction	Report a correction
Record identifier	5c9e5f2f-e987-427a-a147-3f9bc515eded
Record created	2016-10-12
Record modified	2020-06-02

Report a problem on this page

Date modified:: 2020-11-25