A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement

From National Research Council Canada

DOI	Resolve DOI: https://doi.org/10.1109/ASSCC.2007.4425694
Author	Search for: Wey, I-Chyn; Search for: Chen, You-Gang; Search for: Yu, Changhong; Search for: Chen, Jie; Search for: Wu, An-Yeu (Andy)
Format	Text, Article
Conference	IEEE Asian Solid-State Circuits Conference, November 12-14, 2007, Jeju, Korea
Abstract	As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. However, probabilistic-based designs cost larger hardware area. In this paper, we design and implement a hardware-efficient probabilistic-based noise-tolerant circuit, an 8-bit Markov random field carry lookahead adder (MRF_CLA), in 0.13 mum CMOS process technology. The measurement results show that the proposed MRF_CLA can provide 24.5 dB of noise-immunity enhancement as compared with its conventional CMOS design. Moreover, the transistor count can be saved 42% as compared to the state-of-art MRF design
Publication date	2007
In	IEEE Asian Solid-State Circuits Conference, 2007: ASSCC '07; 12-14 Nov. 2007, Jeju City, Korea (2007): 316–319.
Peer reviewed	Yes
NRC publication	This is a non-NRC publication "Non-NRC publications" are publications authored by NRC employees prior to their employment by NRC.
NRC number	504
NPARC number	8926166
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Record identifier	fc285118-2b56-4923-9be2-7662c56ab7c9
Record created	2009-04-23
Record modified	2020-05-10

Date modified:: 2024-10-01