| DOI | Trouver le DOI : https://doi.org/10.1016/0039-6028(94)90971-7 |
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| Auteur | Rechercher : Taylor, R.P.1; Rechercher : Feng, Y.1; Rechercher : Sachrajda, A.S.1; Rechercher : Adams, J.A.1; Rechercher : Davies, M.1; Rechercher : Coleridge, P.T.1; Rechercher : Zawadski, P.1 |
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| Affiliation | - Conseil national de recherches du Canada. Institut des sciences des microstructures du CNRC
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| Format | Texte, Article |
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| Sujet | Electron transitions; Gates (transistor); Semiconducting aluminum compounds; Semiconducting gallium arsenide; Semiconductor device structures; Semiconductor quantum wells; Surfaces; Artificial impurity; Multilevel lateral nano-devices; Quantum dot; Quantum interference effects; Ring geometry; Semiconducting aluminum gallium arsenide; Surface gate patterns; Semiconductor device manufacture |
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| Résumé | The design of surface gate patterns, used to define nanostructurcs in AlGaAs GaAs heterostructures, is greatly enhanced by the possibility of establishing electrical contact to, and independently biasing, a 100 nm wide isolated gate. We describe the fabrication of a multi-level metallisation architecture which can be used to contact a nanoscale central gate and monitor the transition from a quantum dot to ring geometry. We employ geometry induced quantum interference effects as a novel low temperature characterisation tool and report experiments in which the central electrode acts as an artificial impurity. © 1994. |
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| Date de publication | 1994 |
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| Dans | |
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| Langue | anglais |
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| Publications évaluées par des pairs | Oui |
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| Numéro NPARC | 21274634 |
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| Exporter la notice | Exporter en format RIS |
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| Signaler une correction | Signaler une correction (s'ouvre dans un nouvel onglet) |
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| Identificateur de l’enregistrement | 1af138e6-6c21-4920-9cd5-05e5a0adcd1f |
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| Enregistrement créé | 2015-03-18 |
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| Enregistrement modifié | 2020-04-27 |
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