| Download | - View accepted manuscript: Good 150oC Retention and Fast Erase Characteristics in Charge-Trap-Engineered Memory having a Scaled Si3N4 Layer (PDF, 797 KiB)
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| DOI | Resolve DOI: https://doi.org/10.1109/IEDM.2008.4796829 |
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| Author | Search for: Lina, S. H.; Search for: Chin, Albert; Search for: Yeha, F. S.; Search for: McAlister, S. P.1 |
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| Affiliation | - National Research Council of Canada. NRC Institute for Microstructural Sciences
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| Format | Text, Article |
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| Abstract | We report a new charge-trap-engineered flash non-volatile memory that has combined 5 nm Si3N4 and 0.9 nm EOT HfON trapping layers, within double-barrier and double-tunnel layers. At 150degC under a 100 mus and plusmn16 V P/E, this device showed good device integrity of a 5.6 V initial DeltaVth window and 3.8 V 10-year extrapolated retention window. These data are better than the 3.3 V initial DeltaVth and 1.7 V 10-year data for a similar structure not having the extra HfON layer. |
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| Publication date | 2008 |
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| In | |
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| Language | English |
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| Peer reviewed | No |
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| NPARC number | 16891228 |
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| Export citation | Export as RIS |
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| Report a correction | Report a correction (opens in a new tab) |
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| Record identifier | 7e66e906-0f04-40f3-92fc-04c3d1b5522d |
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| Record created | 2011-03-26 |
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| Record modified | 2020-04-15 |
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