| DOI | Trouver le DOI : https://doi.org/10.1109/TNANO.2024.3372946 |
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| Auteur | Rechercher : Ng, Samuel S. H.Identifiant ORCID : https://orcid.org/0000-0001-8061-3074; Rechercher : Croshaw, JeremiahIdentifiant ORCID : https://orcid.org/0000-0001-9164-1556; Rechercher : Walter, MarcelIdentifiant ORCID : https://orcid.org/0000-0001-5660-9518; Rechercher : Wille, RobertIdentifiant ORCID : https://orcid.org/0000-0002-4993-7860; Rechercher : Wolkow, RobertIdentifiant ORCID : https://orcid.org/0000-0001-7850-0548; Rechercher : Walus, KonradIdentifiant ORCID : https://orcid.org/0000-0002-3639-6858 |
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| Bailleur de fonds | Rechercher : Natural Sciences and Engineering Research Council of Canada |
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| Format | Texte, Article |
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| Résumé | Recent research interest in emerging logic systems based on quantum dots has been sparked by the experimental demonstration of nanometer-scale logic devices composed of atomically sized quantum dots made of silicon dangling bonds (SiDBs), along with the availability of SiQAD, a computer-aided design tool designed for this technology. Latest design automation frameworks have enabled the synthesis of SiDB circuits that reach the size of 32×10³nm²—orders of magnitude more complex than their hand-designed counterparts. However, current SiDB simulation engines do not take defects into account, which is important to consider for these sizable systems. This work proposes a formulation for incorporating fixed-charge simulation into established ground state models to cover an important class of defects that has a non-negligible effect on nearby SiDBs at the 10nm scale and beyond. The formulation is validated by implementing it into SiQAD's simulation engine and computationally reproducing experiments on multiple defect types, revealing a high level of accuracy. The new capability is applied towards studying the tolerance of several established logic gates against the introduction of a single nearby defect to establish the corresponding minimum required clearance. These findings are compared against existing metrics to form a foundation for logic robustness studies. |
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| Date de publication | 2024-03-05 |
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| Maison d’édition | Institute of Electrical and Electronics Engineers |
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| Dans | |
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| Langue | anglais |
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| Publications évaluées par des pairs | Oui |
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| Publication du CNRC | Cette publication n’est pas du CNRCCe sont des publications qui ont été rédigées par un auteur du CNRC, mais avant que celui-ci soit employé du CNRC. |
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| Exporter la notice | Exporter en format RIS |
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| Signaler une correction | Signaler une correction (s'ouvre dans un nouvel onglet) |
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| Identificateur de l’enregistrement | c20e4745-ce1b-4ddc-8a92-d564edeecf32 |
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| Enregistrement créé | 2026-01-23 |
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| Enregistrement modifié | 2026-02-25 |
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